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ds05-11056-1e fujitsu semiconductor data sheet memory cmos 2 512 k 16 bit synchronous dynamic ram mb81f161622c-60/-70/-80/-80l cmos 2-bank 524,288-word 16 bit synchronous dynamic random access memory n description the fujitsu mb81f161622c is a cmos synchronous dynamic random access memory (sdram) containing 16,777,216 memory cells accessible in an 16-bit format. the mb81f161622c features a fully synchronous operation referenced to a positive edge clock whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. the mb81f161622c sdram is designed to reduce the complexity of using a standard dynamic ram (dram) which requires many control signal timing constraints, and may improve data bandwidth of memory as much as 5 times more than a conventional dram. the mb81f161622c is ideally suited for laser printers, high resolution graphic adapters, accelerators and other applications where an extremely large memory and bandwidth are required and where a simple interface is needed. n product line & features parameter mb81f161622c reference spec (100mhz @cl=3) -60 -70 -80/-80l cl - t rcd - t rp 3 - 3 - 3 clk min. 3 - 3 - 3 clk min. 3 - 3 - 3 clk min. 3 - 3 - 3 clk min. clock frequency (cl = 3) 167 mhz max. 143 mhz max. 125 mhz max. 100 mhz max. burst mode cycle time (cl = 3) 6.0 ns min. 7.0 ns min. 8.0 ns min. 10 ns min. access time from clock (cl = 3) 5.5 ns max. 6 ns max. 6 ns max. 6 ns max. operating current 150 ma max. 130 ma max. 110 ma max. 90 ma max. power down mode current (i cc2p ) 1 ma max. 1 ma max. 1 ma max. 1 ma max. self refresh mode current (i cc6 ) 1 ma max. 1 ma max. 1 ma / 400 a max. 1 ma max. ? single +3.3 v supply: +0.3 v / - 0.15 v tolerance (-60) 0.3 v tolerance (-70/-80/-80l) ? lvttl compatible i/o interface ? 4 k refresh cycles every 64 ms ? dual banks operation ? burst read/write operation and burst read/single write operation capability ? byte control by dqmu/dqml ? programmable burst type, burst length, and cas latency ? auto-and self-refresh (every 15.6 m s) ? cke power down mode ? output enable and input data mask ? 167 mhz/143mhz/125 mhz clock frequency
2 mb81f161622c-60/-70/-80/-80l n pac k ag e package and ordering information C 50-pin plastic (400 mil) tsop-ii with normal bend leads, order as mb81f161622c- fn (std. power) /- lfn (low power) 50-pin plastic tsop (ii) (fpt-50p-m05) (normal bend) marking side
3 mb81f161622c-60/-70/-80/-80l n pin assignments and descriptions 44 43 42 41 40 39 38 37 36 35 50 49 48 47 46 45 34 33 32 31 30 29 v cc dq 0 dq 1 v ssq dq 2 dq 3 v ccq dq 4 dq 5 v ssq dq 6 dq 7 v ccq dqml we cas ras cs a 11 a 10 /ap a 0 a 1 a 2 a 3 v cc v ss dq 15 dq 14 v ssq dq 13 dq 12 v ccq dq 11 dq 10 v ssq dq 9 dq 8 v ccq du dqmu clk cke du a 9 a 8 a 7 a 6 a 5 a 4 v ss 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 17 18 19 20 21 22 (top view) 50-pin tsop (ii) (marking side) * : these pins are connected internally in the chip. pin number symbol description 1, 7, 13, 25, 38, 44 v cc , v ccq supply voltage 2, 3, 5, 6, 8, 9, 11, 12, 39, 40, 42, 43, 45, 46, 48, 49 dq 0 to dq 15 data i/o ? lower byte: dq 0 to dq 7 ? upper byte: dq 8 to dq 15 4, 10, 26, 41, 47, 50 v ss , v ssq * ground 33, 37 du dont use (leave open) 15 we write enable 16 cas column address strobe 17 ras row address strobe 18 cs chip select 19 a 11 (ba) bank select 20 ap auto precharge enable 20, 21, 22, 23, 24, 27, 28, 29, 30, 31, 32 a 0 to a 10 address input ?row: a 0 to a 10 ? column: a 0 to a 7 34 cke clock enable 35 clk clock input 14, 36 dqml, dqmu input mask/output enable 28 27 26 23 24 25
4 mb81f161622c-60/-70/-80/-80l n block diagram bank-1 v cc v ss /v ssq clk cke a 0 to a 11 , ap dq 0 to dq 15 command decoder address buffer/ register i/o data buffer/ register mode register column address counter ras dram core (2,048 256 16) col. addr. ras cas we cs bank-0 i/o row addr. to each block control signal latch fig. 1 - mb81f161622c block diagram dqml v ccq cas we dqmu clock buffer
5 mb81f161622c-60/-70/-80/-80l n functional truthal table (note *1) command truth table notes *2,*3, and *4 notes: *1. v = valid, l = logic low, h = logic high, x = either l or h *2. all commands assume no csus command on previous rising edge of clock. *3. all commands are assumed to be valid state transitions. *4. all inputs are latched on the rising edge of clock. *5. nop and desl commands have the same effect on the part. unless specifically noted, nop will represent both nop and desl command in later descriptions. *6. read, reada, writ, and writa commands should only be issued after the corresponding bank has been activated (actv command). refer to state diagram. *7. actv command should only be asserted after corresponding bank has been precharged (pre or pall command). *8. required after power up. refer to power-up initialization in page 19. *9. mrs command should only be issued after all banks have been precharged (pre or pall command). refer to state diagram. function notes symbol cke cs ras cas we a 11 (ba) a 10 (ap) a 9 , a 8 a 7 to a 0 n-1 n device deselect *5deslhxhxxxxx x x no operation *5nophx lhhhxx x x burst stop bst h x l h h l x x x x read *6readhxlhlhvl x v read with auto-precharge *6 reada h x l h l h v h x v write *6 writ h x l h l l v l x v write with auto-precharge *6 writa h x l h l l v h x v bank active (ras ) *7 actv h x l l h h v v v v precharge single bank pre h x l l h l v l x x precharge all banks pall h x l l h l x h x x mode register set *8,*9mrshxllllll v v
6 mb81f161622c-60/-70/-80/-80l dqm truth table cke truth table notes: *1. the csus command requires that at least one bank is active. refer to state diagram. nop or desl commands should only be issued after csus and pre (or pall) commands asserted at same time. *2. ref and self commands should only be issued after all banks have been precharged (pre or pal command). refer to state diagram. *3. self and pd commands should only be issued after the last data have been appeared on dq. function command cke dqml dqmu n-1 n data write/output enable for lower byte enbl l h x l x data write/output enable for upper byte enbl u h x x l data mask/output disable for lower byte mask l h x h x data mask/output disable for upper byte mask u h x x h current state function notes symbol cke cs ras cas we a 11 (ba) a 10 (ap) a 9 to a 0 n-1 n bank active clock suspend mode entry *1 csus h l x x x x x x x any except to idle clock suspend continue *1 l l x x x x x x x clock suspend clock suspend mode exit l h x x x x x x x idle auto-refresh command *2 ref h h l l l h x x x idle self-refresh entry *2,*3 self h l l l l h x x x self-refresh self-refresh exit selfx lh l h h h x x x lh h x x x x x x idle power down entry *3 pd hl l h h h x x x hl h x x x x x x power down power down exit lh l h h h x x x lh h x x x x x x
7 mb81f161622c-60/-70/-80/-80l operation command table (applicable to single bank) note *1 (continued) current state cs ras cas we addr command function notes idle hxxx x desl nop lhhh x nop nop l h h l x bst nop l h l h ba, ca, ap read/reada illegal *2 l h l l ba, ca, ap writ/writa illegal *2 l l h h ba, ra actv bank active after t rcd l l h l ba, ap pre/pall nop l l l h x ref/self auto-refresh or self-refresh *3,*6 l l l l mode mrs mode register set (idle after t rsc )*3,*7 bank active h x x x x desl nop lhhh x nop nop l h h l x bst nop l h l h ba, ca, ap read/reada begin read; determine ap l h l l ba, ca, ap writ/writa begin write; determine ap l l h h ba, ra actv illegal *2 l l h l ba, ap pre/pall precharge; determine precharge type l l l h x ref/self illegal l l l l mode mrs illegal
8 mb81f161622c-60/-70/-80/-80l (continued) (continued) current state cs ras cas we addr command function notes read hxxx x desl nop (continue burst to end ? bank active) lhhh x nop nop (continue burst to end ? bank active) l h h l x bst burst stop ? bank active l h l h ba, ca, ap read/reada terminate burst, new read; determine ap l h l l ba, ca, ap writ/writa terminate burst, start write; determine ap *4 l l h h ba, ra actv illegal *2 l l h l ba, ap pre/pall terminate burst, precharge; ? idle determine precharge type l l l h x ref/self illegal l l l l mode mrs illegal write hxxx x desl nop (continue burst to end ? bank active) lhhh x nop nop (continue burst to end ? bank active) l h h l x bst burst stop ? bank active l h l h ba, ca, ap read/reada terminate burst, start read; determine ap *4 l h l l ba, ca, ap writ/writa terminate burst, new write; determine ap l l h h ba, ra actv illegal *2 l l h l ba, ap pre/pall terminate burst, precharge; determine precharge type l l l h x ref/self illegal l l l l mode mrs illegal
9 mb81f161622c-60/-70/-80/-80l (continued) (continued) current state cs ras cas we addr command function notes read with auto- precharge hxxx x desl nop (continue burst to end ? precharge ? idle) lhhh x nop nop (continue burst to end ? precharge ? idle) l h h l x bst illegal l h l h ba, ca, ap read/reada illegal *2 l h l l ba, ca, ap writ/writa illegal *2 l l h h ba, ra actv illegal *2 l l h l ba, ap pre/pall illegal *2 l l l h x ref/self illegal l l l l mode mrs illegal write with auto- precharge hxxx x desl nop (continue burst to end ? precharge ? idle) lhhh x nop nop (continue burst to end ? precharge ? idle) l h h l x bst illegal l h l h ba, ca, ap read/reada illegal *2 l h l l ba, ca, ap writ/writa illegal *2 l l h h ba, ra actv illegal *2 l l h l ba, ap pre/pall illegal *2 l l l h x ref/self illegal l l l l mode mrs illegal
10 mb81f161622c-60/-70/-80/-80l (continued) (continued) current state cs ras cas we addr command function notes precharge h x x x x desl nop (idle after t rp ) l h h h x nop nop (idle after t rp ) l h h l x bst illegal l h l h ba, ca, ap read/reada illegal *2 l h l l ba, ca, ap writ/writa illegal *2 l l h h ba, ra actv illegal *2 l l h l ba, ap pre/pall nop (pall may effect other bank) *5 l l l h x ref/self illegal l l l l mode mrs illegal bank activating h x x x x desl nop (bank active after t rcd ) l h h h x nop nop (bank active after t rcd ) l h h l x bst nop (bank active after t rcd ) l h l h ba, ca, ap read/reada illegal *2 l h l l ba, ca, ap writ/writa illegal *2 l l h h ba, ra actv illegal *2 l l h l ba, ap pre/pall illegal *2 l l l h x ref/self illegal l l l l mode mrs illegal
11 mb81f161622c-60/-70/-80/-80l (continued) abbreviations: ra = row address ba = bank address ca = column address ap = auto precharge notes: *1. all entries assume the cke was high during the proceeding clock cycle and the current clock cycle. illegal means dont used command. if used, power up sequence be asserted after power shout down. *2. illegal to bank in specified state; entry may be legal in the bank specified by ba, depending on the state of that bank. *3. illegal if any bank is not idle. *4. must satisfy bus contention, bus turn around, and/or write recovery requirements. refer to timing diagram - 11 & - 12. *5. nop to bank precharging or in idle state. may precharge bank specified by ba (and ap). *6. self command should only be issued after the last read data have been appeared on dq. *7. mrs command should only be issued on condition that all dq are in hi-z. current state cs ras cas we addr command function notes refreshing h x x x x desl nop (idle after t rc ) l h h x x nop/bst nop (idle after t rc ) lhlx x read/reada/ writ/writa illegal llhx x actv/pre/ pall illegal lllx x ref/self/ mrs illegal mode register setting h x x x x desl nop (idle after t rsc ) l h h h x nop nop (idle after t rsc ) l h h l x bst illegal lhlx x read/reada/ writ/writa illegal llxx x actv/pre/ pall/ref/ self/mrs illegal
12 mb81f161622c-60/-70/-80/-80l command truth table for cke note *1 (continued) current state cke n-1 cke n cs ras cas we addr function notes self- refresh hxxxxx x invalid lhhxxx x exit self-refresh (self-refresh recovery ? idle after t rc ) lhlhhh x exit self-refresh (self-refresh recovery ? idle after t rc ) l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal l lxxxx x nop (maintain self-refresh) self- refresh recovery lxxxxx x invalid h h h x x x x idle after t rc h h l h h h x idle after t rc h h l h h l x illegal h h l h l x x illegal h h l l x x x illegal hhxxxx x illegal hlxxxx x illegal *2
13 mb81f161622c-60/-70/-80/-80l (continued) (continued) current state cke n-1 cke n cs ras cas we addr function notes power down hxxxxx x invalid l h h x x x x exit power down mode ? idle l h l h h h x exit power down mode ? idle l lxxxx x nop (maintain power down mode) l h l l x x x illegal l h l h l x x illegal both banks idle h h h x x x mode refer to the operation command table h h l h x x mode refer to the operation command table h h l l h x mode refer to the operation command table h h l l l h x auto-refresh hhllll moderefer to the operation command table h l h x x x x power down h l l h h h x power down h l l h h l x illegal h l l h l x x illegal h l l l h x x illegal hllllh x self-refresh *3 hlllll x illegal lxxxxx x invalid
14 mb81f161622c-60/-70/-80/-80l (continued) notes: *1. all entries in command truth table for cke are specified at cke(n) state and cke input from cke(nC1) to cke(n) state must satisfy corresponding set up and hold time for cke. *2. cke should be held high for t rc period. *3. self command should only be issued after the last data have been appeared on dq. current state cke n-1 cke n cs ras cas we addr function notes bank active bank activating read/write hhxxxx x refer to the operation command table hlxxxx x begin clock sus pend next cycle lxxxxx x invalid clock suspend hxxxxx x invalid lhxxxx x exit clock suspend next cycle l lxxxx x maintain clock suspend any state other than listed above hhxxxx x refer to the operation command table hlxxxx x illegal lxxxxx x invalid
15 mb81f161622c-60/-70/-80/-80l n functional description sdram basic function three major differences between this sdram and conventional drams are: synchronized operation, burst mode, and mode register. the synchronized operation is the fundamental difference. an sdram uses a clock input for the synchronization, where the dram is basically asynchronous memory although it has been using two clocks, ras and cas . each operation of dram is determined by their timing phase differences while each operation of sdram is determined by commands and all operations are referenced to a positive clock edge. fig.2 shows the basic timing diagram differences between sdrams and drams. the burst mode is a very high speed access mode utilizing an internal column address generator. once a column addresses for the first access is set, following addresses are automatically generated by the internal column address counter. the mode register is to justify the sdram operation and function into desired system conditions. mode register table shows how sdram can be configured for system requirement by mode register programming. clock (clk) and clock enable (cke) all input and output signals of sdram use register type buffers. a clk is used as a trigger for the register and internal burst counter increment. all inputs are latched by a positive edge of clk. all outputs are validated by the clk. cke is a high active clock enable signal. when cke = low is latched at a clock input during active cycle, the next clock will be internally masked. during idle state (all banks have been precharged), the power down mode(standby) is entered with cke = low and this will make extremely low standby current. chip select (cs ) cs enables all commands inputs, ras , cas , and we , and address input. when cs is high, command signals are negated but internal operation such as burst cycle will not be suspended. if such a control isnt needed, cs can be tied to ground level. command inputs (ras , cas and we ) unlike a conventional dram, ras , cas , and we do not directly imply sdram operation, such as row address strobe by ras . instead, each combination of ras , cas , and we input in conjunction with cs input at a rising edge of the clk determines sdram operation. refer to functional truth table in page 5. address inputs (a 0 to a 10 ) address input selects an arbitrary location of a total of 524,288 words of each memory cell matrix. a total of 19 address input signals are required to decode such a matrix. sdram adopts an address multiplexer in order to reduce the pin count of the address line. at a bank active command (actv), 11 row addresses are initially latched and the remainder of 8 column addresses are then latched by a column address strobe command of either a read command (read or reada) or write command (writ or writa). bank select (a 11 ) this sdram has two banks and each bank is organized as 512 k words by 16-bit. bank selection by a 11 occurs at bank active command (actv) followed by read (read or reada), write (writ or writa), and precharge command (pre).
16 mb81f161622c-60/-70/-80/-80l data inputs and outputs (dq 0 to dq 15 ) input data is latched and written into the memory at the clock following the write command input. data output is obtained by the following conditions followed by a read command input: t rac : from the bank active command when t rcd (min) is satisfied. (this parameter is reference only.) t cac : from the read command when t rcd is greater than t rcd (min).(this parameter is reference only.) t ac : from the clock edge after t rac and t cac . the polarity of the output data is identical to that of the input. data is valid between access time (determined by the three conditions above) and the next positive clock edge (t oh ). data i/o mask (dqml/dqmu) dqml and dqmu are active high enable inputs and have an output disable and input mask function. during burst cycle and when dqml/dqmu = high is latched by a clock, input is masked at the same clock and output will be masked at the second clock later while internal burst counter will increment by one or will go to the next stage depending on burst type. dqml controls lower byte (dq 0 to dq 7 ) and dqmu controls upper byte (dq 8 to dq 15 ). burst mode operation and burst type the burst mode provides faster memory access. the burst mode is implemented by keeping the same row address and by automatic strobing column address. access time and cycle time of burst mode is specified as t ac and t ck , respectively. the internal column address counter operation is determined by a mode register which defines burst type and burst count length of 1,2,4 or 8 bits of boundary. in order to terminate or to move from the current burst mode to the next stage while the remaining burst count is more than 1, the following combinations will be required: the burst type can be selected either sequential or interleave mode if burst length is 2,4 or 8. the sequential mode is an incremental decoding scheme within a boundary address to be determined by count length, it assigns +1 to the previous (or initial) address until reaching the end of boundary address and then wraps round to least significant address(=0). the interleave mode is a scrambled decoding scheme for a 0 and a 2 . if the first access of column address is even (0), the next address will be odd (1), or vice-versa. (continued) current stage next stage method (assert the following command) burst read burst read read command burst read burst write 1st step mask command (normally 3 clock cycles) 2nd step write command after l owd burst write burst write write command burst write burst read read command burst read precharge precharge command burst write precharge precharge command
17 mb81f161622c-60/-70/-80/-80l (continued) when the full burst operation is executed at single write mode, auto-precharge command is valid only at write operation. the burst type can be selected either sequential or interleave mode. but only the sequential mode is usable to the full column burst. the sequential mode is an incremental decoding scheme within a boundary address to be determined by burst length, it assigns +1 to the previous (or initial) address until reaching the end of boundary address and then wraps round to least significant address(=0). full column burst and burst stop command (bst) the full column burst is an option of burst length and available only at sequential mode of burst type. this full column burst mode is repeatedly access to the same column. if burst mode reaches end of column address, then it wraps round to first column address (=0) and continues to count until interrupted by the news read (read) /write (writ), precharge (pre), or burst stop (bst) command. the selection of auto-precharge option is illegal during the full column burst operation except write command at burst read & single write mode. the bst command is applicable to terminated burst operation. if the bst command is asserted burst mode, its operation is terminated immediately and the internal state moves to bank active. when read mode is interrupted by bst command, the output will be in high-z. for the detail rule, please refer to timing diagram-8. when write mode is interrupted by bst command, the data to be applied at the same time with bst command will be ignored. burst read & single write the burst read and single write mode provides single word write operation regardless of its burst length. in this mode, burst read operation does not affected by this mode. burst length stating column address a 2 a 1 a 0 sequential mode interleave 2 x x 0 0 - 1 0 - 1 x x 1 1 - 0 1 - 0 4 x 0 0 0 - 1 - 2 - 3 0 - 1 - 2 - 3 x 0 1 1 - 2 - 3 - 0 1 - 0 - 3 - 2 x 1 0 2 - 3 - 0 - 1 2 - 3 - 0 - 1 x 1 1 3 - 0 - 1 - 2 3 - 2 - 1 - 0 8 0 0 0 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 0 0 1 1 - 2 - 3 - 4 - 5 - 6 - 7 - 0 1 - 0 - 3 - 2 - 5 - 4 - 7 - 6 0 1 0 2 - 3 - 4 - 5 - 6 - 7 - 0 - 1 2 - 3 - 0 - 1 - 6 - 7 - 4 - 5 0 1 1 3 - 4 - 5 - 6 - 7 - 0 - 1 - 2 3 - 2 - 1 - 0 - 7 - 6 - 5 - 4 1 0 0 4 - 5 - 6 - 7 - 0 - 1 - 2 - 3 4 - 5 - 6 - 7 - 0 - 1 - 2 - 3 1 0 1 5 - 6 - 7 - 0 - 1 - 2 - 3 - 4 5 - 4 - 7 - 6 - 1 - 0 - 3 - 2 1 1 0 6 - 7 - 0 - 1 - 2 - 3 - 4 - 5 6 - 7 - 4 - 5 - 2 - 3 - 0 - 1 1 1 1 7 - 0 - 1 - 2 - 3 - 4 - 5 - 6 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0
18 mb81f161622c-60/-70/-80/-80l precharge and precharge option (pre, pall) sdram memory core is the same as conventional drams, requiring precharge and refresh operations. precharge rewrites the bit line and to reset the internal row address line and is executed by the precharge command (pre). with the precharge command, sdram will automatically be in standby state after precharge time (t rp ). the precharged bank is selected by combination of ap and a 11 when precharge command is asserted. if ap = high, both banks are precharged regardless of a 11 (pall). if ap = low, a bank to be selected by a 11 is precharged (pre). the auto-precharge enters precharge mode at the end of burst mode of read or write without precharge command assertion. this auto-precharge is entered by ap = high when a read or write command is asserted. refer to function truth table. auto-refresh (ref) auto-refresh uses the internal refresh address counter. the sdram auto-refresh command (ref) generates precharge command internally. all banks of sdram should be precharged prior to the auto-refresh command. the auto-refresh command should also be asserted every 15.6 m s or a total 4096 refresh commands within a 64 ms period. self-refresh entry (self) self-refresh function provides automatic refresh by an internal timer as well as auto-refresh and will continue the refresh function until cancelled by selfx. the self-refresh is entered by applying an auto-refresh command in conjunction with cke = low (self). once sdram enters the self-refresh mode, all inputs except for cke will be dont care (either logic high or low level state) and outputs will be in a high-z state. during a self-refresh mode, cke = low should be maintained. self command should only be issued after last read data has been appeared on dq. note: when the burst refresh method is used, a total of 4096 auto-refresh commands within 4 ms must be asserted prior to the self-refresh mode entry. self-refresh exit (selfx) to exit self-refresh mode, apply minimum t cksp after cke brought high, and then the nop command (nop) or the deselect command (desl) should be asserted within minimum t rc . refer to timing diagram for the detail. it is recommended to assert an auto-refresh command just after the t rc period to avoid the violation of refresh period. note: when the burst refresh method is used, a total of 4096 auto-refresh commands within 4 ms must be asserted after the self-refresh exit. mode register set (mrs) the mode register of sdram provides a variety of different operations. the register consists of four operation fields; burst length, burst type, cas latency, and operation code. refer to mode register table in page 33. the mode register can be programmed by the mode register set command (mrs). each field is set by the address line. once a mode register is programmed, the contents of the register will be held until re-programmed by another mrs command (or part loses power). mrs command should only be issued on condition that all dq is in hi-z. the condition of the mode register is undefined after the power-up stage. it is required to set each field after initialization of sdram. refer to power-up initialization below.
19 mb81f161622c-60/-70/-80/-80l power-up initialization the sdram internal condition after power-up will be undefined. it is required to follow the following power on sequence to execute read or write operation. 1. apply power and start clock. attempt to maintain either nop or desl command at the input. 2. maintain stable power, stable clock, and nop condition for a minimum of 200 m s. 3. precharge all banks by precharge (pre) or precharge all command (pall). 4. assert minimum of 2 auto-refresh command(ref). 5. program the mode register by mode register set command(mrs). in addition, it is recommended dqml/dqmu and cke to track v cc to insure that output is high-z state. the mode register set command (mrs) can be set before 2 auto-refresh command (ref).
20 mb81f161622c-60/-70/-80/-80l fig. 2 C basic timing for conventional dram vs. synchronous dynamic ram ras cas dq clk cs dq t si ras cas cke we cas latency = 2 burst length = 4 active read/write precharge t hi h : read l : write ba (a 11 ) ra ba (a 11 ) ca ba (a 11 ) ap (a 10 ) row address select column address select h h address h precharge
21 mb81f161622c-60/-70/-80/-80l mode register set self refresh idle read suspend bank active auto refresh power down bank active suspend fig. 3 C state diagram (simplified for single bank operation state diagram) write write suspend power on precharge read read with auto precharge writ read read writ mrs self selfx ref actv cke cke\(pd) cke\ cke cke\ cke read writ reada writa reada cke\ cke writa pre or pall pre or pa l l power applied definition of allows manual input automatic sequence writa reada pre or pa l l pre or pa l l write with auto precharge cke\ cke read suspend write suspend cke\ cke
22 mb81f161622c-60/-70/-80/-80l n 1 bank operation command table minimum clock latency or delay time for 1 bank operation notes: *1. assume no i/o conflict. *2. if t rp t ck, minimum latency is a sum of bl + cl. *3. assume output is in high-z state. *4. assume t ras is satisfied. second command (same bank) mrs actv read reada writ writa pre pall ref self first command mrs t rsc t rsc t rsc t rsc t rsc t rsc actv t rcd *4 t rcd t rcd *4 t rcd t ras t ras read 11 *1 1 *1 1 11 reada *2 bl + t rp *2 bl + t rp *2 bl + t rp *2 bl + t rp writ t wr t wr 11t dpl t dpl writa t dal t dal t dal t dal pre *3 t rp *3 t rp t rp t rp *3 t rp *3 t rp pall *3 t rp *3 t rp t rp t rp *3 t rp *3 t rp ref t rc t rc t rc t rc t rc t rc selfx t rc t rc t rc t rc illegal command
23 mb81f161622c-60/-70/-80/-80l n multi bank operation command table minimum clock latency or delay time for 2 bank operation notes: *1. assume opposite bank is in idle state. *2. assume opposite bank is in active state. *3. assume no i/o conflict. *4. if t rp t ck, minimum latency is a sum of bl + cl. *5. assume pall command dose not affect any operation on opposite bank. *6. assume output is in high-z state. *7. assume t ras of opposite bank is satisfied. *8. assume t ras (actv to pall) is satisfied. *9. if opposite bank should be interrupted, t ras of own bank is satisfied.. second command (opposite bank) mrs actv read reada writ writa pre pall ref self first command mrs t rsc t rsc t rsc t rsc t rsc t rsc actv *1 t rrd *2 1 *2 1 *2 1 *2 1 *7 1 t ras read *1 1 *2 1 *2 1 *2 *3 1 *2 *3 1 *7 1 *8 1 *9 reada *1 *4 bl + t rp *1 1 11111 *1 *4 bl + t rp *1 *4 bl + t rp writ *1 1 *2 1 *2 1 *2 1 *2 1 *7 1 *8 1 *9 writa *1 *4 bl + t rp *1 1 11111 *1 bl + 1 + t rp *1 bl + 1 + t rp pre *1 t rp *1 1 *2 1 *2 1 *2 1 *2 1 1t ras *1 t rp *1 t rp pall t rp *1 t rp 11 *1 *6 t rp *1 *6 t rp ref t rc t rc t rc t rc t rc t rc selfx t rc t rc t rc t rc illegal command
24 mb81f161622c-60/-70/-80/-80l n mode register table 1 2 4 8 reserved reserved reserved full column reserved 2 4 8 reserved reserved reserved reserved bt = 0 bt = 1 * 2 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 address 0 0 cl bt bl mode register a 2 a 1 a 0 burst length a 3 burst type sequential (wrap round, binary-up) interleave (wrap round, binary-up) 0 1 a 6 a 5 a 4 cas latency 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 mode register set reserved reserved 2 3 reserved reserved reserved reserved a 11 a 10 0 0 op- code a 9 op-code burst read & burst write burst read & single write * 1 0 1 notes: *1.when a 9 = 1, burst length at write is always one regardless of bl value. *2.bl = 1 and full column are not applicable to the interleave mode.
25 mb81f161622c-60/-70/-80/-80l n absolute maximum ratings (see warning) warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n recommended operating conditions (referenced to v ss ) notes: warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within these recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. n capacitance (t a = 25 c, f = 1 mhz) parameter symbol value unit voltage of v cc supply relative to v ss v cc C0.5 to +4.6 v voltage at any pin relative to v ss v in , v out C0.5 to +4.6 v short circuit output current i out C50 to +50 ma power dissipation p d 1.3 w storage temperature t stg C55 to +125 c parameter notes symbol min. typ. max. unit supply voltage -60 v cc , v ccq 3.15 3.3 3.6 v -70/-80-/80l v cc , v ccq 3.0 3.3 3.6 v v ss , v ssq 000v input high voltage *1 v ih 2.0 v cc + 0.5 v input low voltage *2 v il C0.5 0.8 v ambient temperature t a 070 c parameter symbol min. typ. max. unit input capacitance, except for clk c in1 2.5 5 pf input capacitance for clk c in2 2.5 4 pf i/o capacitance c i/o 4.0 6.5 pf *2. undershoot limit: v il (min) 4.6 v v ih v il pulse width 5 ns *1. overshoot limit: v ih (max) 50% of pulse amplitude v ih v il C 1.5v pulse width measured at 50% of pulse amplitude. = 4.6 v for pulse width <= 5 ns acceptable, = v ss C1.5 v for pulse width <= 5 ns acceptable, pulse width measured at 50% of pulse amplitude. 50% of pulse amplitude pulse width 5 ns v ih min v il max
26 mb81f161622c-60/-70/-80/-80l n dc characteristics (at recommended operating conditions unless otherwise noted.) notes *1, *2, and *3 (continued) parameter symbol conditions value unit min. max. output high voltage v oh(dc) i oh = C2 ma 2.4 v output low voltage v ol(dc) i ol = 2 ma 0.4 v input leakage current (any input) i li 0 v v in v cc ; all other pins not under test = 0 v C5 5 a output leakage current i lo 0 v v in v cc ; data out disabled C5 5 a operating current (average power supply current) mb81f161622c-60 i cc1s burst: length = 4, t rc = min for bl = 4, t ck = min, one bank active, outputs open, addresses changed up to 3-times during t rc (min), 0 v v in v cc v ccq current is included. 150 ma mb81f161622c-70 130 mb81f161622c-80/-80l 110 reference spec (100mhz @cl=3) 90 precharge standby current (power supply current) i cc2p cke = v il , all banks idle, t ck = min, power down mode, 0 v v in v cc 1ma mb81f161622c -60/-70/-80 i cc2ps cke = v il , all banks idle, clk = h or l, power down mode, 0 v v in v cc 1ma mb81f161622c-80l 400 a mb81f161622c-60 i cc2n cke = v ih , all banks idle, t ck = min, nop commands only, input signals (except to cmd) are changed one times during 3 clock cycles, 0 v v in v cc 20 ma mb81f161622c-70 20 mb81f161622c-80/-80l 20 reference spec (100mhz @cl=3) 15 i cc2ns cke = v ih , all banks idle, clk = h or l, input signals are stable, 0 v v in v cc 2 *4 *4
27 mb81f161622c-60/-70/-80/-80l (continued) notes: *1. all voltages are referred to v ss . *2. dc characteristics are measured after following the power-up initialization procedure. *3. i cc depends on the output termination or load condition, clock cycle rate, signal clocking rate. the specified values are obtained with the output open and no termination register. *4. this value is for reference only. parameter symbol conditions value unit min. max. active standby current (power supply current) i cc3p cke = v il , any bank active, t ck = min, 0 v v in v cc 1ma mb81f161622c -60/-70/-80 i cc3ps cke = v il , any bank active, clk = h or l, 0 v v in v cc 1ma mb81f161622c-80l 400 a active standby current (power supply current) mb81f161622c-60 i cc3n cke = v ih , any bank active, t ck = min, nop commands only, input signals (except to cmd) are changed one times during 3 clock cycles, 0 v v in v cc 35ma mb81f161622c-70 30 ma mb81f161622c-80/-80l 30 ma reference spec (100mhz @cl=3) 20ma i cc3ns cke = v ih, any bank active, clk = h or l, 0 v v in v cc 2ma burst mode current (average power supply current) mb81f161622c-60 i cc4 t ck = min, burst length = 4, outputs open, multiple-banks active, gapless data, 0 v v in v cc v ccq current is included. 185 ma mb81f161622c-70 160 mb81f161622c-80/-80l 145 reference spec (100mhz @cl=3) 120 refresh current #1 (average power supply current) mb81f161622c-60 i cc5 auto-refresh; t ck = min, t rc = min, 0 v v in v cc 80 ma mb81f161622c-70 70 mb81f161622c-80/-80l 60 reference spec (100mhz @cl=3) 55 refresh current #2 (average power supply current) mb81f161622c -60/-70/-80 i cc6 self-refresh; t ck = min, cke 0.2 v, 0 v v in v cc 1ma mb81f161622c-80l 400 a *4 *4 *4
28 mb81f161622c-60/-70/-80/-80l n ac characteristics (at recommended operating conditions unless otherwise noted.) notes *1, *2, and *3 parameter notes sym bol mb81f161622c -60 mb81f161622c -70 mb81f161622c -80/-80l reference spec (100mhz@cl=3) unit min. max. min. max. min. max. min. max. clock period cas latency = 2 t ck2 10.5 12 15 ns cas latency = 3 t ck3 6.0 7.0 8 10 ns clock high time *5 t ch 2.5 2.5 3 3 ns clock low time *5 t cl 2.5 2.5 3 3 ns input setup time *5 t si 2 2 2.5 2.5 ns input hold time *5 t hi 111 1 ns access time from clock (t ck = m i n ) *5,*6,*7 cas latency = 2 t ac2 7 7 7ns cas latency = 3 t ac3 5.5 6 6 6ns output in low-z *5 t lz 000 0 ns output in high-z *5,*8 cas latency = 2 t hz2 2727 2 7ns cas latency = 3 t hz3 25.52626 2 6ns output hold time *5,*7 cas latency = 2 t oh 2 2 2 ns cas latency = 3 2 2 2 2 ns time between auto-refresh command interval *4 t refi 15.6 15.6 15.6 15.6 s transition time t t 0.5 10 0.5 10 0.5 10 0.5 10 ns cke setup time for power down exit *5 t cksp 333 3 ns * 4
29 mb81f161622c-60/-70/-80/-80l base values for clock count/latency clock count formula note *10 parameter notes symbol mb81f161622c -60 mb81f161622c -70 mb81f161622c -80/-80l reference spec (100mhz@cl=3) unit min. max. min. max. min. max. min. max. ras cycle time *9 t rc 54.0 63.0 72 80 ns ras precharge time t rp 18.0 21.0 24 30 ns ras active time t ras 36 100000 42 100000 48 100000 50 100000 ns ras to cas delay time t rcd 18.0 21.0 24 30 ns write recovery time t wr 6.0 7.0 8 10 ns data-in to precharge lead time t dpl 6.0 7.0 8 10 ns data-in to active/refresh command period cas latency = 2 t dal2 1cyc+t rp 1cyc+t rp 1cyc+t rp ns cas latency = 3 t dal3 2cyc+t rp 2cyc+t rp 2cyc+t rp 2cyc+t rp ns mode register set cycle time t rsc 12 14 16 20 ns ras to ras bank active delay time t rrd 12 14 16 20 ns clock 3 clock period base value (round off a whole number) * 4
30 mb81f161622c-60/-70/-80/-80l latency-fixed values (the latency values on these parameters are fixed regardless of clock period.) notes: *1. ac characteristics are measured after following the power-up initialization procedure. *2. ac characteristics assume t t = 1 ns and 30 pf of terminated load. *3. 1.4 v is the reference level for measuring timing of input signals. transition times are measured between v ih (min) and v il (max). *4. this value is for reference only. *5. if input signal transition time (t t ) is longer than 1 ns; [(t t /2) C 0.5] ns should be added to t ac (max), t hz (max), and t cksp (min) spec values, [(t t /2) C 0.5] ns should be subtracted from t lz (min), t hz (min), and t oh (min) spec values, and (t t C 1.0) ns should be added to t ch (min), t cl (min), t si (min), and t hi (min) spec values. *6. t ac also specifies the access time at burst mode. *7. t ac and t oh are the spec value under ac test load circuit shown in fig. 4. *8. specified where output buffer is no longer driven. *9. actual clock count of t rc (l rc ) will be sum of clock count of t ras (l ras ) and t rp (l rp ). *10. all base values are measured from the clock edge at the command input to the clock edge for the next command input. all clock counts are calculated by a simple formula: clock count equals base value divided by clock period (round off to a whole number). parameter notes sym- bol mb81f161622c -60 mb81f161622c -70 mb81f161622c -80/-80l reference spec (100mhz@cl=3) unit cke to clock disable l cke 1 1 1 1 cycle dqm to output in high-z l dqz 2 2 2 2 cycle dqm to input data delay l dqd 0 0 0 0 cycle last output to write command delay l owd 2 2 2 2 cycle write command to input data delay l dwd 0 0 0 0 cycle precharge to output in high-z delay cl = 2 l roh2 2 2 2 cycle cl = 3 l roh3 3 3 3 3 cycle burst stop command to output in high-z delay cl = 2 l bsh2 2 2 2 cycle cl = 3 l bsh3 3 3 3 3 cycle cas to cas delay (min) l ccd 1 1 1 1 cycle cas bank delay (min) l cbd 1 1 1 1 cycle * 4
31 mb81f161622c-60/-70/-80/-80l fig. 4 C example of ac test load circuit r 1 = 50 w c l = 30 pf lvttl output 1.4 v note: ac characteristics are measured in this condition. this load circuits are not applicable for v oh and v ol .
32 mb81f161622c-60/-70/-80/-80l fig. 5 C timing diagram, setup, hold and delay time note: reference level of input signal is 1.4 v for lvttl. access time is measured at 1.4 v for lvttl. t si t ch t ck t ac t hz t oh t lz t cl clk input (control, addr. & data) output 2.4 v 1.4 v 0.4 v 1.4 v 2.4 v 0.4 v 1.4 v 2.4 v 0.4 v t hi fig. 6 C timing diagram, delay time for power down exit clk cke t cksp (min) nop dont care dont care command 1 clock (min) nop actv
33 mb81f161622c-60/-70/-80/-80l fig. 7 C timing diagram, pulse width fig. 8 C timing diagram, access time t rc , t rp , t ras , t rcd , t wr , t ref , t dpl , t dal , t rsc , t rrd , t cksp command command clk input (control) note: these parameter are a limit value of the rising edge of the clock from one command input to next input. t cksp is the latency value from the rising edge of cke. measurement reference voltage is 1.4 v. t ac (cas latency C 1) t ck clk commnd dq (output) q(valid) read t ac q(valid) q(valid) t ac
34 mb81f161622c-60/-70/-80/-80l n timing diagrams timing diagram - 1 : clock enable - read and write suspend (@ bl = 4) notes: *1. the latency of cke (l cke ) is one clock. *2. during read mode, burst counter will not be incremented/decremented at the next clock of csus command. output remain the same data. *3. during the write mode, data at the next clock of csus command is ignored. q1 q2 (no change) q3 (no change) q4 d1 not written d2 not written d3 d4 clk cke clk (internal) dq (read) dq (write) *1 *2 *3 *3 i cke (1 clock) i cke (1 clock) timing diagram - 2 : clock enable - power down entry and exit notes: *1. precharge command (pre or pall) should be asserted if any bank is active and in the burst mode. *2. precharge command can be posted in conjunction with cke when burst mode is ended at this clock. *3. the actv command can be latched after t cksp (min) + 1clock (min). it is should be asserted nop command in conjunction with cke. *4.the actv command can be latched after t cksp (min.) + 1 clock(min.). nop pd(nop) dont care nop actv clk cke command 1 clock (min) *1 *2 *3 nop *3 t cksp t ref (max) *1 *2 *2 *2 *4
35 mb81f161622c-60/-70/-80/-80l timing diagram - 3 : column address to column address input delay note: cas to cas address delay can be one or more clock period. timing diagram - 4 : different bank address input delay t rcd (min) clk ras cas row address column address address column address column address column address i ccd column address i ccd (1 clock) i ccd i ccd clk ras cas row address row address address column address column address column address bank 0 bank 1 bank 1 bank 1 bank 0 bank 0 a 11 (ba) column address t rrd (min) t rcd (min) t rcd (min) i cbd i cbd
36 mb81f161622c-60/-70/-80/-80l timing diagram - 5 : dqm-input mask and output disable (@ bl = 4) timing diagram - 6 : precharge timing (applied to the same bank) clk dqml-dqmu (@ read) dq (@ read) dqml-dqmu (@ write) dq (@ write) q1 q2 hi-z q4 end of burst d1 masked d3 d4 end of burst i dqz (2 clocks) i dqd (same clock) clk command precharge actv t ras (min) note: precharge means pre or pall.
37 mb81f161622c-60/-70/-80/-80l timing diagram - 7 : read interrupted by precharge (example @ cl = 2, bl = 4) note: in case of cl = 2, the l roh is 2 clock. in case of cl = 3, the l roh is 3 clock. precharge means pre or pall. clk command dq command dq command dq command dq hi-z q1 precharge precharge precharge precharge q1 q2 q1 q2 q3 q1 q2 q3 q4 hi-z hi-z no effect (end of burst) i roh (2 clocks) i roh (2 clocks) i roh (2 clocks)
38 mb81f161622c-60/-70/-80/-80l timing diagram - 8 : read interrupted by burst stop (example @ bl = full column) timing diagram - 9 : write interrupt by burst stop (example @ cl = 2) note: the selection of auto-precharge option is illegal during the full column burst operation except write command at burst read & single write mode. clk command (cl = 2) dq command (cl = 3) dq hi-z hi-z bst bst q n C 2 q n C 1 q n q n + 1 q n C 2 q n C 1 q n q n + 1 q n + 2 i bsh (3 clocks) i bsh (2 clocks) clk command dq last data-in masked by bst bst command
39 mb81f161622c-60/-70/-80/-80l timing diagram - 10 : write interupted by precharge (example @ cl = 3) notes: * 1.the precharge command (pre) should only be issued after the t dpl of final data input, is satisfied. *2.precharge means pre or pall. clk command dq precharge active data-in masked by pre t dpl (min) t rp (min) last data-in timing diagram - 11 : read interrupted by write (example @ cl = 3, bl = 4) notes: * 1.first dqm makes high-impedance state high-z between last output and first input data. *2.second dqm makes internal output data mask to avoid bus contention. *3.third dqm in illustrated above also makes internal output data mask. if burst read ends (final data output) at or after the second clock of burst write, this third dqm is required to avoid internal bus contention. clk command dqm (dqml/dqmu) dq data out masked data in data in *1 *2 *3 write i dwd (same clock) read i owd (2 clocks) i dqz (2 clocks) *1 *2
40 mb81f161622c-60/-70/-80/-80l timing diagram - 12 : write to read timing (example @ cl = 3, bl = 4) note: *1. read command should be issued after t wr of final data input is satisfied if read command is applied to the same bank. clk command dqm (dqml/dqmu) dq write read d1 q1 q2 d3 t wr (min) d2 t ac (max) masked by read (clC1) t ck *1
41 mb81f161622c-60/-70/-80/-80l timing diagram - 13 : read with auto-precharge (example @ cl = 2, bl = 2 applied to same bank) notes: * 1. precharge at read with auto-precharge command (reada) is started from number of clocks that is the same as burst length (bl) after reada command is asserted. *2. next actv command should be issued after bl + t rp (min) from reada command. timing diagram - 14 : write with auto-precharge *1,*2,*3 (example @ cl = 2, bl = 2 applied to same bank) notes: * 1. precharge at write with auto-precharge is started after the t dpl from the end of burst. *2. even if the final data is masked by dqm, the precharge does not start the clock of final data input. *3. once auto precharge command is asserted, no new command within the same bank can be issued. *4. auto-precharge command doesnt affect at full column burst operation except burst read & single write mode. *5. next command should be issued after bl + t rp (min) at cl = 2, bl + 1+ t rp (min) at cl = 3 from writea command. clk command dq reada actv nop or desl dqm (dqml/dqmu) actv q1 q2 t ras (min) (same value as bl) t rp (min) clk command dq writa actv nop or desl dqm (dqml/dqmu) actv d1 d2 t dal (min) 2 clocks *1 bl + t rp (min) *2 t ras (min) 1 bl + t rp (min) *5 t dpl (min) *4
42 mb81f161622c-60/-70/-80/-80l timing diagram - 15 : auto-refresh timing notes: *1. all banks should be precharged prior to the first auto-refresh command (ref). *2. bank select is ignored at ref command. the refresh address and bank select are selected by internal refresh counter. *3. either nop or desl command should be asserted during t rrd and t rc period while auto-refresh mode. *4. any activation command such as actv or mrs command other than ref command should be asserted after t rc from the last ref command. timing diagram - 16 : self-refresh entry and exit timing notes: *1. precharge command (pre or pall) should be asserted if any bank is active prior to self-refresh entry command (self). *2. the self-refresh exit command (selfx) is latched after t cksp (min). it is recommended to apply nop command in conjunction with cke. it is also recommended to apply minimum of 4 clocks to stabilize external clock prior to selfx command. *3. either nop or desl command can be used during t rc period. *4. cke should be held high within t rc (min) period after t cksp clk command a 11 (ba) command dont care dont care ba nop ref nop *4 dont care t rc (min) t rc (min) clk cke command nop self dont care selfx command nop *2 nop *3 *1 t cksp (min) ref nop *3 nop *3 *1 t rc (min) *4 *3 *2 t si (min) *3
43 mb81f161622c-60/-70/-80/-80l timing diagram - 17 : mode register set timing note: the mode register set command (mrs) should be only asserted after all banks have been precharged. clk command address mrs nop or desl mode row address actv t rsc
44 mb81f161622c-60/-70/-80/-80l n package dimension 50-pin plastic tsop (ii) (fpt-50p-m05) (.045.002) 1.150.05 lead no. 0.10(.004) max 0.40(.016) max 0.15(.006) 0.25(.010) details of "a" part (.005.002) 0.1250.05 (.400.004) 10.160.10 (.463.008) 11.760.20 (.424.008) 10.760.20 (.020.004) 0.500.10 (stand off) 0.05(.002)min 0.10(.004) typ. 0.80(.031) ref. 19.20(.756) * 0.13(.005) m (.012.004) 0.300.10 (.825.004) 20.950.10 index "a" 25 1 26 50 1995 fujitsu limited f50005s-2c-1 c dimensions in mm (inches) * resin protrusion. (each side: 0.15 (.006) max)
mb81f161622c-60/-70/-80/-80l fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-8588, japan tel: 81(44) 754-3763 fax: 81(44) 754-3329 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, usa tel: (408) 922-9000 fax: (408) 922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: (800) 866-8608 fax: (408) 922-9179 http://www.fujitsumicro.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10 d-63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 http://www.fujitsu-ede.com/ asia pacific fujitsu microelectronics asia pte ltd #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 http://www.fmap.com.sg/ f9910 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan.

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